A defect in one processing tile can affect the usability of a larger AI chip. Xilinx therefore describes an array with at least one additional spare column. US application US20260311794A1 was published on October 8, 2026. Its aim is to keep chips with localized defects usable.
Rerouting before computation
The array consists of interconnected tiles with computing, memory and communication resources. At startup, a built-in self-test checks the tiles; alternatively, the hardware reads a defect indicator programmed during factory testing. A bypass circuit isolates the affected column and redirects data, computational tasks and memory connections to the spare. Internal addresses are adjusted so software still sees a contiguous memory space. In the described example, an array with three usable columns receives a fourth as a replacement. Without a defect, this spare remains inactive.
Independent claim 1 in the original document covers the arrangement; claims 2–5 specify defect detection, switches, control logic and isolation. Paragraphs [0031]–[0035] explain the spare column, self-test and factory indicator.
The limit is at startup
The specifically described switchover occurs only at boot: This mechanism does not handle faults that arise after initialization. A single spare column is also insufficient for multiple defective columns. More spares require additional silicon area and switching logic. The document supplies no measured yield, cost or performance figures and establishes no available product.
Document and status
“Artificial Intelligence Engine Array with Redundant Column”: Applicant XILINX, INC.; US application 19/169,617, filed April 3, 2025. The cover lists no earlier priority. A1 denotes an application publication. We could not independently confirm the current official prosecution status on October 10, 2026; a grant is therefore not established.
Pandorex View: The approach turns additional computing area into a manufacturing reserve. Whether that pays off depends on defect rates and the cost of the spare. Assessing it requires chip measurements and yield data; describing a rerouting path alone does not answer that question.