Intel aims to arrange standard cells so their layout can accommodate power delivery from either the front or back of a chip. US application US20260304889A1, published on October 1, 2026, uses power vias along cell boundaries. These repeatable cells form the building blocks of digital logic.
Connections at the boundary
Conductive vias pass through the insulating layer beside the transistors' source/drain regions. Frontside contacts connect these regions to the vias; backside metal layers connect underneath. The connections can be vertically aligned. Intel thus describes a cell geometry supporting either power-delivery direction. This does not mean every chip must be powered from both sides simultaneously. Examples in the document include a two-transistor inverter and NAND and NOR cells. The focus is the arrangement of connections within the cell's limited space.
The geometry is supported by the original document, paragraphs [0020]–[0022], Figure 1A/1B, independent claim 14 and dependent claims 17–20.
A layout proposal, not a performance result
The document demonstrates no measured improvements in power consumption, area, manufacturing yield or voltage drop. Its drawings are schematic. Associating it with a specific process node or processor would also be unsupported. Whether the arrangement actually saves design work would need to be checked against real cell libraries, fabrication rules and reliability tests.
Document and status
“Standard Cell Architecture with Frontside and Backside Power Via Connections”: Applicant Intel Corporation; US application 19/091,305, filed March 26, 2025. The cover lists no earlier priority. A1 denotes a published application, not a grant. We could not independently confirm the current official prosecution status on October 3, 2026.
Pandorex View: Reusing a cell layout when changing power-delivery direction would be interesting. The application makes that approach tangible; it does not yet demonstrate an economic or technical benefit in a finished chip.